In typical multilayer semiconductor integrated circuits including several layers of interconnect wiring, the uppermost layers typically include metal bonding pads for forming electrical connection with the semiconductor device (chip) surface to a package which contains the chip. The bonding pads are typically formed in an array on the chip surface which in turn forms an array on a process wafer surface.
Prior to cutting the process wafer into the various constituent chips, the semiconductor wafer surface including the bonding pads are covered with one or more passivation layers to provide electrical insulation between the conducting areas and to physically protect the chip surface to prevent absorption of moisture or other contaminants.
The passivation layers must first be patterned and etched to form openings over the bonding pads in order to make the bonding pads accessible to subsequent bonding operations.
Recently, it has been the practice to use a polyimide as an uppermost passivation layer on the process wafer surface after patterning and etching an opening through an underlying passivation layer over the bonding pads. A polyimide resin is excellent in electrical and mechanical characteristics, including high heat resistance and is advantageously used as a surface-protecting and insulation layer for a semiconductor device.
One problem with prior art processes using polyimide has been the tendency of the polyimide to shrink in volume up to about 50 percent following a curing process to remove solvent, making a one mask patterning process unreliable to achieve the same pattern in the polyimide and the underlying passivation layer.
Various approaches in the prior art have been proposed for the process flow of patterning and etching to overcome the problems of polyimide shrinking. However, another problem that has presented itself is the tendency for the polyimide to leave a polyimide residue on the underlying passivation layer following a curing process, thereby degrading subsequent bonding operations, reducing a chip yield. For example, subsequently formed bonds to the bonding pad surface exhibit a high rate of failure due to poor adhesion.
There is therefore is a need in the integrated circuit manufacturing process art to develop a passivation layer patterning and etching process to improve a patterning process and reduce bonding pad contamination to improve chip yield and performance while improving a process flow.
It is therefore an object of the invention to provide an improved passivation layer patterning and etching process to improve a patterning process and reduce bonding pad contamination to improve chip yield and performance while improving a process flow, in addition to overcoming other shortcomings of the prior art.